Reduction of the error in the hardware neural network

Dhafer r. Zaghar

Article Details

Reduction of the error in the hardware neural network

Authors:

Dhafer r. Zaghar

Publisher:

University of Baghdad

Journal:

Al-Khwarizmi Engineering Journal Vol.3 Issue 2, pp.1-7

Document Type:

Article

Publication Date:

1/2007

Document Language:

English

Document ID (Org No.):

2001539049

pISSN:

2312-0789

Abstract:

 Specialized hardware implementations of Artificial Neural Networks (ANNs) can offer faster execution than general-purpose microprocessors by taking advantage of reusable modules, parallel processes and specialized computational components. Modern high-density Field Programmable Gate Arrays (FPGAs) offer the required flexibility and fast design-to-implementation time with the possibility of exploiting highly parallel computations like those required by ANNs in hardware. The bounded width of the data in FPGA ANNs will add an additional error to the result of the output. This paper derives the equations of the additional error value that generate from bounded width of the data and proposed a method to reduce the effect of the error to give an optimal result in the output with a low cost.

Article Details

Reduction of the error in the hardware neural network

Authors: Dhafer r. Zaghar

Publisher: University of Baghdad

Journal: Al-Khwarizmi Engineering Journal Vol.3 Issue 2, pp.1-7

Document Type: Article

Publication Date: 1/2007

Document Language: English

Document ID (Org No.): 2001539049

pISSN: 2312-0789

Issues

Authors:

Dhafer r. Zaghar

Publisher:

University of Baghdad

Journal:

Al-Khwarizmi Engineering Journal Vol.3 Issue 2, pp.1-7

Document Type:

Article

Publication Date:

1/2007

Document Language:

English

Document ID (Org No.):

2001539049

pISSN:

2312-0789